FPGA Simulated Annealing Accelerator

Technical Summary

Jonathan Phillips and Aravind Dasu, researchers at Utah State University, have developed a pipelined processor that provides opportunities to design circuits customized to accelerate autonomous-scheduling algorithms. Current microprocessors are struggling to meet demand for on-board autonomy-enabling applications. The most popular solution, application specific integrated circuits (ASICs), have been able to meet application demands, but at a very high cost. The inventors have developed a technology that improves upon Field Programmable Gate Arrays (FPGAs), an alternative method of supporting on-board autonomy-enabling applications that is more flexible and has a lower cost. 

 

Commercial Applications

Interested companies would include computer manufacturers and chip designers.

 

Competitive Advantages

•  Low cost compared to other solutions 

•  Flexible enough to allow for algorithmic changes

 

References

•  See U.S. Patent 8,296,120

•  “A C to register transfer level algorithm using structured circuit templates: a case study with simulated annealing” by Jonathan D. Phillips

 

Patent Information:
Category(s):
Computer Science Electrical and Electronics
For Information, Contact:
Christian Iverson
Utah State University
435-797-9620
christian.iverson@usu.edu
Inventors:
Aravind Dasu Jonathan Phillips
Keywords: