DARP: Dynamically Adaptable Resilient Pipeline Design in Microprocessors

Developed by Hu Chen, Dr. Sanghamitra Roy, and Dr. Koushik Chakraborty of Utah State University’s Electrical and Computer Engineering Department

 

Technical Summary

Rapid miniaturization of transistor devices has introduced several uncertainties in their operation. Modern microprocessor pipelines experience multiple sources of delay variations, sometimes manifesting as timing errors, process variation, and aging. To ensure reliable operation while preserving energy efficiency under delay variation, two of the most popular techniques applied on microprocessor pipelines are timing speculation and clock skew tuning. Some recent works tackle process variation and aging based delay variation in a purely static timing analysis but do not address the delay variance in real world applications.

 

USU researchers have employed a circuit-architectural analysis to investigate and exploit the delay variation seen in sensitized circuit paths during real world application execution. Two distinct classes of variations were identified: (a) temporal-delay variation within a given pipe stage during different phases of a program and (b) spatial-delay distributions among different pipe stages of a microprocessor.

 

By combining early error prediction with clock skew tuning, a next wave innovation, Dynamically Adaptable Resilient Pipeline (DARP), pushes the energy efficient frontier of pipelined microprocessor design. In addition to handling the well-studied delay variations from process variation and again, DARP can adapt a pipeline to the spatial and temporal delay variations in real workloads. DARP employs program phase driven early timing error prediction and dynamic frequency and clock skew adjustment to exploit workload specific delay characteristics in pipelined systems.

 

Competitive Advantages

Compared to state-of-the-art timing speculation techniques, DARP schemes improve performance by 9.4-20% and energy efficiency by 6.4-27.9%. DARP schemes also have negligible core level power overheads of 0.84% and 3.35%, giving an energy efficient alternative for robust pipelines. The researchers tested these DARP schemes using rigorous circuit-architectural simulation and combining synthesized hardware with real world application execution through architectural simulation.

 

Commercial Applications

•  Microprocessor optimization

 

References

•  Hu Chen; Roy, S.; Chakraborty, K., "DARP: Dynamically Adaptable Resilient Pipeline design in microprocessors," in Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , vol., no., pp.1-6, 24-28 March 2014    doi: 10.7873/DATE.2014.075

 

Patent Information:
Category(s):
Computer Science
For Information, Contact:
Christian Iverson
Utah State University
435-797-9620
christian.iverson@usu.edu
Inventors:
Hu Chen Sanghamitra Roy Koushik Chakraborty
Keywords: